1. Field of the Invention
The present invention relates to a module comprising flip chip devices forming at least the semiconductor portion of a circuit.
2. Description of the Related Art
Numerous types of electrical circuits, such as DC to DC converters, synchronous converters, and the like, require a number of semiconductor components such as MOSFETs and ICs. Such circuit components can be found in portable electronics apparatus and the support components are commonly separately housed and mounted individually on a support board. The separately housed parts take up board space and each part generates heat. If the part is near other components, such as microprocessors, the part can interfere with the operation of the microprocessor.
To address the twin problems of heat generation and the occupation of board space, at least two different approaches have been applied previously.
One approach has been to arrange various semiconductor components in a planar fashion in a single housing. An exemplary circuit diagram, including semiconductor components, which are arranged in a planar fashion on a single substrate, is shown in FIG. 1, which was originally shown as FIG. 2 of U.S. Pat. No. 6,388,319.
FIG. 1 shows a synchronous buck converter circuit having an N-channel MOSFET 4 as a switching device, and an N-channel synchronous MOSFET 5 and a Schottky diode 6 in parallel for synchronous rectification. The N-channel MOSFET 4, N-channel MOSFET 5, and Schottky diode 6 are arranged in a planar fashion within a common housing 7. However, the control circuit 8 connected to the gates of MOSFETs 4 and 5 is not contained within the previously mentioned common housing 7. Since the source (top) of die 4 is connected to the drain (bottom) of die 5, it was required to insulate die 5 from the substrate, and wire bond. In addition, control chip 8 was separate because it had to be insulated from the board.
Other patents taking the approach of arranging semiconductor components in a planar fashion within a common housing include U.S. Pat. Nos. 5,977,630, 6,144,093, 6,404,050, 6,448,643, 6,465,875, 6,593,622, and 6,696,321. Significantly, however, in all of the references previously cited, wire bonding was used extensively to make the necessary connections between the semiconductor components. Such wire bonding leads to higher resistance and inductance. Additionally, although packaging the components in a common housing reduces the thermal effects of the components when compared to the components being housed separately, further improvement in thermal management is desirable.
A second approach toward confronting the problems of occupation of board space and thermal management involves the use of stacked or superimposed die contained within a common housing. Such an approach is exemplified by U.S. Pat. Nos. 5,770,480, 6,798,044 and 6,858,922. Such an approach should conserve board space even more than the planar arrangement approach. In addition, wire bonding between the die can be eliminated. However, such an approach may involve increases in the thermal effects the operation of one die would have on the other die stacked or superimposed on it over the planar arrangement approach.